1. Field of the Invention
The present invention generally relates to content-address memory cells (referred to simply as CAM cell hereinafter), and more particularly, to a content-address memory cell which stores data and has a bit matching function to detect match or mismatch between the stored data and retrieval data for output.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing a conventional CAM cell as disclosed in "IEEE Journal of Solid-State Circuits, Vol. SC--7, pp. 366" (U.S. Pat. No. 3,701,980). In the diagram, a CAM cell 6 is connected to a word line 1, a bit line 2a, an inverted-bit line 2b and a match line 3. The CAM cell 6 comprises a data storage portion 7, a data comparison portion 8 and an n-channel MOS transistor 10. The data storage portion 7 comprises two n-channel MOS transistors 13a and 13b, and the data comparison portion 8 comprises two n-channel MOS transistors 14a and 14b. The n-channel MOS transistor 13a is connected between the bit line 2a and the gate of the n-channel MOS transistor 14a, and the n-channel MOS transistor 13b is connected between the inverted-bit line 2b and the gate of the n-channel MOS transistor 14b. Further, the respective gates of these n-channel MOS transistors 13a and 13b are both connected to the word line 1. The n-channel MOS transistor 14a is connected between the bit line 2a and a control terminal 16, and the n-channel MOS transistor 14b is connected between the inverted-bit line 2b and the control terminal 16. Further, the n-channel MOS transistor 10 is connected between the match line 3 and the control terminal 16 and has the gate connected also to the match line 3. Therefore, the n-channel MOS transistor 10 serves as a diode. Meanwhile, the match line 3 has parasitic capacitance (capacitance value C.sub.M).
In the following, operation of the conventional CAM cell shown in FIG. 1 will be described for the respective cases of writing, matching and reading, with reference to FIGS. 2 to 4.